neue files für die tisch pwm. nur zum angucken, übersetzt noch nicht alles.

schaltung/muxtisch/Makefile

+all: muxtisch_tb
+
+muxtisch.o: multipwm.o
+muxtisch_tb.o:	muxtisch.o
+
+muxtisch_tb:	muxtisch_tb.o muxtisch.o
+	ghdl -e test_tisch #muxtisch_tb
+
+%.o : %.vhd
+	ghdl -a $<
+clean:
+	rm muxtisch_tb.o muxtisch.o

schaltung/muxtisch/multipwm.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    11:02:24 02/05/2012 
+-- Design Name: 
+-- Module Name:    dampfmascine - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity multipwm is
+  generic (
+     N : natural := 16;                 -- bit width of pwm
+     P : natural := 33);                 -- PWM rows
+  Port  ( takt : in  STD_LOGIC;
+          pwm : in  STD_LOGIC_VECTOR (N*P-1 downto 0);
+          led : out  STD_LOGIC_VECTOR (P-1 downto 0));
+end multipwm;
+
+
+architecture Behavioral of multipwm is
+ -- single counter for all pwms
+ signal ct: natural range ((2**N)-1) downto 0:=0;
+
+ begin
+   counter: process( takt )
+   begin
+     if( rising_edge( takt ) ) then
+       ct<= ct+1;
+     end if;
+   end process counter;
+
+   -- purpose: PWM-Vergleicher für eine spalte LEDs
+   -- type   : combinational
+   -- inputs : ct,pwm
+   -- outputs: led
+   cmp: process (ct,pwm)
+   begin  -- process cmp
+     for R in 0 to P-1 loop
+       if( ct<unsigned(pwm( R*(N+1)-1 downto R*N)) ) then led(R) <= '1';
+       else
+         led(R)<='0';
+       end if;
+     end loop;  -- R
+   end process cmp;
+ end Behavioral;

schaltung/muxtisch/muxtisch.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    11:02:24 02/05/2012 
+-- Design Name: 
+-- Module Name:    dampfmascine - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+ entity muxmaschine is
+  generic (
+    N : natural := 16;                 -- bit width of pwm
+    P : natural := 33;                 -- PWM rows
+    C : natural := 24);                 -- PWM columns
+  Port  ( takt   : in  STD_LOGIC;
+          data   : in  STD_LOGIC_VECTOR ( 7 downto 0);
+          address : in STD_LOGIC_VECTOR ( 10 downto 0);  -- hackhack
+          ledout  : out STD_LOGIC_VECTOR (P-1 downto 0);
+          columnv: out STD_LOGIC_VECTOR (C-1 downto 0));
+end muxmaschine;
+
+architecture Behavioral of muxmaschine is
+
+  signal coltakt: STD_LOGIC :='0';
+  signal column : natural range 0 to C-1;
+  signal pwmspalte : STD_LOGIC_VECTOR ( P-1 downto 0 );
+
+begin
+  inst_multipwm: entity work.multipwm(Behavioral)
+    generic map (
+      N => 16,
+      P => 33)
+    port map (
+      takt => takt,
+      pwm  => pwmspalte,
+      led  => ledout);
+  
+alles: process( takt )
+  begin
+end process alles;
+end Behavioral;

schaltung/muxtisch/muxtisch_tb.vhd

+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+entity test_tisch is
+end test_tisch;
+
+architecture testbench of test_tisch is
+  component muxmaschine is
+    generic (
+      N : natural := 4;                 -- bit width of pwm
+      P : natural := 3;                 -- PWM rows
+      C : natural := 24);                 -- PWM columns
+    Port  ( takt : in  STD_LOGIC;
+            pwm : in  STD_LOGIC_VECTOR (N*P-1 downto 0);
+            led : out  STD_LOGIC_VECTOR (P-1 downto 0));
+  end component muxmaschine;
+
+  signal clk : STD_LOGIC := '0';
+  signal data : STD_LOGIC_VECTOR (4*3-1 downto 0);
+  signal outputs : STD_LOGIC_VECTOR (3-1 downto 0);
+begin  -- testbench
+
+  TST : muxmaschine port map (
+    takt => clk,
+    pwm  => data,
+    led  => outputs );
+  TST_P: process
+    begin
+    end process;
+end testbench;

schaltung/muxtisch/pwmcolumncnt.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    11:02:24 02/05/2012 
+-- Design Name: 
+-- Module Name:    dampfmascine - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+ entity pwmcolumncnt is
+  generic (
+    C : natural := 24);                 -- PWM columns
+  Port  ( ctakt   : in  STD_LOGIC;
+          columns : out  STD_LOGIC_VECTOR (C-1 downto 0));
+end pwmcolumncnt;
+
+architecture Behavioral of pwmcolumncnt is
+  signal ctakt: STD_LOGIC :=0;
+  signal column : natural range 0 to C-1;
+begin
+colcounter: process( coltakt )
+   begin
+     if( rising_edge( coltakt ) ) then
+       column<= column+1;
+     end if;
+   end process colcounter;
+
+end Behavioral;

schaltung/muxtisch/ram.vhd

+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+enity pwmram is
+  generic (
+    OW: natural := 33*16;
+    )
+  port (
+    taktin: STD_LOGIC;
+    din: STD_LOGIC_VECTOR ( 7 downto 0 );
+    ain: STD_LOGIC_VECTOR ( 10 downto 0);
+    taktout: STD_LOGIC;
+    dout: STD_LOGIC_VECTOR ( 511 downto 0);
+    aout: STD_LOGIC_VECTOR ( 4 downto 0 ));
+
+
+
+
+architecture behavioral of pwmram is
+
+begin  -- behavioral
+
+  lesen: process( taktout )
+    begin
+      if( rising_edge( taktout )) then
+        dout<=ramdata(aout);
+      end if;
+    end process;
+    schreiben: process( taktin )
+      begin
+        if( rising_edge( taktin )) then
+          ramdata(ain)<=din;
+        end if;
+      end process;
+end behavioral;