ram.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

enity pwmram is
  generic (
    OW: natural := 33*16;
    )
  port (
    taktin: STD_LOGIC;
    din: STD_LOGIC_VECTOR ( 7 downto 0 );
    ain: STD_LOGIC_VECTOR ( 10 downto 0);
    taktout: STD_LOGIC;
    dout: STD_LOGIC_VECTOR ( 511 downto 0);
    aout: STD_LOGIC_VECTOR ( 4 downto 0 ));




architecture behavioral of pwmram is

begin  -- behavioral

  lesen: process( taktout )
    begin
      if( rising_edge( taktout )) then
        dout<=ramdata(aout);
      end if;
    end process;
    schreiben: process( taktin )
      begin
        if( rising_edge( taktin )) then
          ramdata(ain)<=din;
        end if;
      end process;
end behavioral;